K3N3C3000D-D(G)C CMOS MASK ROM 4M-Bit (512Kx8) CMOS MASK ROM FEATURES GENERAL DESCRIPTION * 524,288x8 bit organization * Access time : 80ns(Max.) * Supply voltage : single +5V * Current consumption Operating : 50mA(Max.) Standby : 50A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package -. K3N3C3000D-DC : 32-DIP-600 -. K3N3C3000D-GC : 32-SOP-525 The K3N3C3000D-D(G)C is a fully static mask programmable ROM organized 524,288 x 8 bit. It is fabricated using silicon gate CMOS process technology. This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3N3C3000D-DC is packaged in a 32-DIP and the K3N3C3000D-GC in a 32-SOP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION A18 . . . . . . . . A0 X BUFFERS AND DECODER MEMORY CELL MATRIX (524,288x8) Y BUFFERS AND DECODER SENSE AMP. N.C 1 32 VCC A16 2 31 A18 A15 3 30 A17 A12 4 29 A14 A7 5 28 A13 A6 6 A5 7 A4 8 A3 9 BUFFERS . . . CE Q0 CONTROL LOGIC OE Pin Name Pin Function A0 - A18 Address Inputs Q0 - Q 7 Data Outputs CE Chip Enable OE Output Enable VCC Power(+5V) VSS Ground N.C No Connection Q7 27 A8 DIP & SOP 26 A9 25 A11 24 OE A2 10 23 A10 A1 11 21 CE A0 12 21 Q7 Q0 13 20 Q6 Q1 14 19 Q5 Q2 15 18 Q4 VSS 16 17 Q3 K3N3C3000D-D(G)C K3N3C3000D-D(G)C CMOS MASK ROM ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit VIN -0.3 to +7.0 V Voltage on Any Pin Relative to VSS Temperature Under Bias TBIAS -10 to +85 C Storage Temperature TSTG -55 to +150 C NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C) Symbol Min Typ Max Unit Supply Voltage Item VCC 4.5 5.0 5.5 V Supply Voltage VSS 0 0 0 V DC CHARACTERISTICS Parameter Operating Current Symbol Test Conditions Min Max Unit ICC Cycle=5MHz, all outputs open CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) - 50 mA Standby Current(TTL) ISB1 CE=VIH, all outputs open - 1 mA Standby Current(CMOS) ISB2 CE=VCC, all outputs open - 50 A Input Leakage Current ILI VIN=0 to VCC - 10 A Output Leakage Current ILO VOUT=0 to VCC - 10 A Input High Voltage, All Inputs VIH 2.2 VCC+0.3 V Input Low Voltage, All Inputs VIL -0.3 0.8 V Output High Voltage Level VOH IOH=-400A 2.4 - V Output Low Voltage Level VOL IOL=2.1mA - 0.4 V NOTE : Minimum DC Voltage(V IL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage(VIH ) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. MODE SELECTION CE OE Mode Data Power H X Standby High-Z Standby H Operating High-Z Active L Operating Dout Active Symbol Test Conditions Min Max Unit COUT VOUT=0V - 10 pF CIN VIN=0V - 10 pF L CAPACITANCE(TA=25C, f=1.0MHz) Item Output Capacitance Input Capacitance NOTE : Capacitance is periodically sampled and not 100% tested. K3N3C3000D-D(G)C CMOS MASK ROM AC CHARACTERISTICS(TA=0C to +70C, VCC=5V10%, unless otherwise noted.) TEST CONDITIONS Item Value Input Pulse Levels 0.6V to 2.4V Input Rise and Fall Times 10ns Input and Output timing Levels 0.8V and 2.0V Output Loads 1 TTL Gate and CL=100pF READ CYCLE Item Symbol K3N3C3D-D(G)C08 Min K3N3C3D-D(G)C10 Max Min 80 Max 100 K3N3C3D-D(G)C12 Min Max Read Cycle Time tRC Chip Enable Access Time tACE 80 100 120 ns Address Access Time tAA 80 100 120 ns Output Enable Access Time tOE 40 50 60 ns Output or Chip Disable to Output High-Z tDF 20 20 20 ns Output Hold from Address Change tOH 0 120 Unit 0 ns 0 ns TIMING DIAGRAM READ ADD1 ADD ADD2 tRC tDF(Note) tACE CE tOE tAA OE tOH D OUT VALID DATA VALID DATA NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.